Back end of line (BEOL) process is generally used in integrated circuit (IC) fabrication process to connect active or passive devices with wirings on the wafer. In the BEOL process, multiple interconnect levels which include interconnect and via contacts, dielectric layers, contact pads and bonding sites for chip to package connections are formed. We have discovered that punch through tends to occur between interconnects in adjacent interconnect level during semiconductor processing, leading to inter-level metal electrical short. This is undesirable as it renders the IC malfunction.
From the foregoing discussion, there is a need to provide more reliable interconnects and a simplified method to form such reliable interconnects.